1. Field of the Invention
This invention relates to methods and apparatus for chemical/mechanical planarization (CMP) of a semiconductor substrate. More particularly, this invention relates to methods and apparatus to planarize a semiconductor substrate having shallow trench isolation while reducing dishing and minimizing erosion of silicon nitride on the surface of the semiconductor substrate.
2. Description of Related Art
Chemical/mechanical planarization (CMP) of a semiconductor substrate is well known in the art. A description of CMP is found in ULSI Technology, Chang and Sze, McGraw-Hill Co. Inc., New York, N.Y., 1996, pp. 434-439 and is shown in FIG. 1. The requirements for polishing a dielectric are the removal of material while maintaining uniformity across the entire semiconductor substrate. The CMP involves the use of chemistry as well as mechanical abrasion for the removal of material.
A polishing station 100 of CMP machine is equipped with a rotating platen 5. A polishing pad 10 is attached to the platen S. A semiconductor substrate 20 is secured to the wafer carrier 15. The wafer carrier 15 is lowered to place the semiconductor substrate 20 in contact with the polishing pad 10. The wafer carrier 16 is rotated at a speed independent of the platen 5 and the wafer carrier 15 is adjusted to exert force on the platen 5.
A polishing slurry 25 is delivered from the slurry supply 30 to ensure uniform wetting of the polishing pad 10 as well as proper delivery and recovery of the polishing slurry 25. The polishing slurry 25 consists primarily of colloidal silica suspended in a solution of potassium hydroxide (KOH).
A CMP machine will have multiple polishing stations 100 connected by automated cassette-to-cassette handlers and automatic wafer loaders.
The basic polishing mechanism for polishing silicon dioxide (SiO.sub.2) dielectric is the same as for glass polishing. The mechanical removal rate is given by Preston's equation: EQU R=K.sub.p pv
where:
R is the rate of removal of material, PA1 p is the applied pressure between the semiconductor substrate 20 and the platen 5, PA1 v is the relative velocity between the semiconductor substrate 20 and the platen 5, and PA1 K.sub.p is a constant of proportionality.
Preston's constant K.sub.p is a function of the mechanical properties of the silicon dioxide dielectric such as hardness and Young's modulus, the polishing slurry, and the structure of the polishing pad.
The above equation is a mechanical description of the rate of removal of material during planarization. However, the microscopic action of polishing is both chemical and mechanical. The exact mechanism of polishing is currently not well understood, but the present description of polishing divides the chemical process into four stages. In the first stage, hydrogen bonds with the oxide surfaces of the semiconductor substrate 20. The second step has the hydrogen bonds of the slurry 25 and semiconductor substrate 20 joining together. In the third step, the silicon of the slurry 25 and the semiconductor substrate 20 are bonded to a common oxygen atom to form a molecular bond. The fourth step has the slurry 25 moving away transporting the molecular silicon with it, thus removing material from the surface of the semiconductor substrate 20.
The above described stages have three important implications: Polishing is not just abrasion of the silica of the slurry 25 against the semiconductor substrate 20. The presence of water and the PH of the solution affect the formation of hydrogen bonds. Further, the size and composition of the particles of the slurry 25 determine the effectiveness. The most common particulate used in the slurry 25 is silica with a particle size of 10 nanometers to 90 nanometers.
It is apparent from Preston's equation that the rate of removal R is directly related to the applied pressure p and the velocity v of platen. The rate of removal of material as shown in FIG. 4 and the selectivity of the chemical/mechanical planarization polishing as shown in FIG. 5 are generally plotted versus the product of platen pressure and platen speed.
Refer now to FIGS. 2a and 2b for a discussion of the problems associated with the current CMP practice of prior art for polishing a semiconductor substrate having shallow trench isolation (STI). A semiconductor substrate 200 has a layer of silicon dioxide SiO.sub.2 210 formed on the top surface. On the layer of SiO.sub.2 layer 210, a layer of Silicon Nitride Si.sub.x N.sub.y is deposited to form a planarization stop layer 215.
A photolithographic mask (not shown) is formed on the planarization stop layer 215. The photolithographic mask is exposed to create a pattern for the shallow trenches 205a, 205b, 205c, and 205d that are to be created on the surface of the semiconductor substrate 200. The areas that are to be the shallow trenches 205a, 206b, 205c, and 205d are removed from the photolithographic mask. The surface of the semiconductor substrate 200 is exposed to an etchant to remove the planarization stop layer 215, the SiO.sub.2 layer 210, and a portion of the semiconductor substrate 200 to thus form the shallow trenches 205a, 205b, 205c, and 205d. A SiO.sub.2 fill 220 is deposited on the surface of the semiconductor substrate 200. The deposition of the SiO.sub.2 fill is generally accomplished by a chemical vapor deposition of ozone-Tetraethylorthosilane (O.sub.3.spsp.- TEOS) or by a Spin-On-Glass (SOG) process that is well known in the art. The SiO.sub.2 fill 220 is then removed by a CMP process as described above.
The SiO.sub.2 fill 220 is intended to be removed until the surface is level with the planarization stop layer 215. However, the CMP process of the prior art causes three types of problems at the surface of the semiconductor substrate 200. The first problem is shown in FIG. 2b section I. The surface of the semiconductor substrate 200 is over polished causing erosion and thus a thinning of the Si.sub.x N.sub.y planarization stop layer 215.
The second problem is illustrated in FIG. 2b section II. The surface of the semiconductor substrate 200 is again over polished, however in this instance irregularities in the platen causes over polishing which causes dishing. The dishing is caused in areas of large shallow trenches 205c, and 205d and entirely removes the planarization stop layer 207.
The third problem is shown in FIG. 2b section III. Areas of the surface of the semiconductor substrate 200 are under polished. This leaves areas of SiO.sub.2 fill 220 on the surface of the planarization stop layer 215.
U.S. Pat. No. 5,575,706 (Tsai et al.), assigned to the same assignee as this invention, discloses an improved and new apparatus and process for chemical mechanical planarization (CMP) of a semiconductor wafer surface. The polish removal rate is controlled through the application of an electric field between the semiconductor wafer carrier and the polishing pad. Further, application of an electric field between selected regions of the semiconductor wafer carrier and polishing pad affects the polish removal rates in a manner which improves the uniformity of material removal across the entire semiconductor wafer surface The uniformity of polish removal rate is further controlled through the application of bi-directional electric fields between the semiconductor wafer carrier and the polishing pad.
The novel features of the polishing apparatus of Tsai et al. is applying an electric field between the wafer carrier and polishing platen as a means of controlling the concentration of the polishing slurry across the surface of the semiconductor wafer being polished. The control of the concentration of the slurry and thus of the polish removal rate will improve the uniformity of polish removal rate across the semiconductor wafer surface.
U.S. Pat. No. 4,671,851 (Beyer et al) discloses a method for removing the aspirates, typically the ridge-shaped SiO.sub.2 protuberances (so-called "bird's heads") resulting from the ROI process at the surface of the silicon substrate. The invention is accomplished by applying CMP to the surface of the silicon substrate. The silicon substrate has been previously coated with a blanket polishing stop barrier layer, typically of CVD (Chemical Vapor Deposition) of a Si.sub.3 N.sub.4 layer. The portions of the Si.sub.3 N.sub.4 layer, located on the curved top of the "bird's heads" and the underlying SiO.sub.2 protuberances, are removed because they are submitted to a considerably higher CMP polishing rate than the portions covering the planar substrate surface. This CVD Si.sub.x N.sub.y layer unexpectedly acts therefore as a polishing or etch stop barrier layer only on the planar portions of the substrate surface. The difference between these polishing rates may be varied simply by controllably applying different pressure magnitudes on the polishing pad. A successful planarization of the protuberances by a CMP polishing process depends on the polishing solution chemistry. In that respect, SiO.sub.2 water based slurries have demonstrated their efficiency. Polishing rate ratios between SiO.sub.2 and Si.sub.3 N.sub.4 preferably should be between a lower limit of four to one and a higher limit of forty to one.
U.S. Pat. No. 5,665,202 (Subramanian et al.) teaches a process for polish planarizing a fill material overlying a semiconductor substrate. In one embodiment, a second planarization layer is deposited over a fill material and a portion of the fill material is removed leaving a remaining portion. The pad pressure of a CMP apparatus is adjusted such that a first pressure is generated during the polishing process. Then, the remaining portion is removed, while operating the CMP apparatus at a second pressure. The selectivity of the polishing process is maintained by reducing the pad pressure during the second polishing step. In a second embodiment, after the first polishing step is performed, the remaining portion of the fill material is removed by an etching process using a portion of the second planarization layer.